L6717ATR datasheet(27/57 Pages) STMICROELECTRONICS

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L6717A

Power manager I2C

L6717A features a secondary power manager I

C bus to easy the implementation of power

management features as well as overspeeding for “enthusiastic” users. The power manager

C bus is operative after the PWRGOOD signal is driven high at the end of the soft-start.

Power manager I

C is a two wire, SCL (Clock) and SDA (Data), bus that connects a single

master to one or more slaves (L6717A) separately addressable. The master initiates and

terminates I

C transactions and drives the clock, SCL, and the data, SDA, during a

transaction. The slave receives the I

C transactions and acts accordingly. Power manager

C wire protocol is based on fast-mode I

Power manager I

C Address configuration can be programmed through ADDR pin while

I2CDIS pin allow disabling the bus See

Table 10.

Power manager I

C and SVI bus are two independent buses working in parallel. In case two

commends are issued in the same time on the two buses, L6717A performs them in the

same time.

6.1

Power manager commands

Power manager I

C master issues different command sequences to modify several

parameters in the CORE section and/or the NB section of L6717A. In the same way, power

manager I

C command are able to configure DPM and other power-saving-related features.

During a

power manager command:

–

The bus master sends the start (START) sequence followed by the

Address of the

Controller which the

power manager command applies. The bus master then sends

the write (WRITE) bit. After the write bit, the voltage regulator (VR, L6717A) sends the

acknowledge (ACK) bit.

–

The bus master sends the command code during the

command phase. The VR

(L6717A) sends the acknowledge (ACK) bit after the command phase.

–

The bus master sends the

data stream related to the command phase previously

issued (if applicable). The VR (L6717A) sends the acknowledge (ACK) bit after the

data stream. Finally, the bus master sends the stop (STOP) sequence.

–

After the VR (L6717A) has detected the STOP sequence, it performs operations

according to the command issued by the bus master.

Refer to

Figure 9, Table 11 and Table 12 for details.

Table 10. Power manager I2C configuration

I2CDIS

ADDR

Description

3.3V

n/a

Power manager

C disabled.

SDA/OVP now becomes OVP to program the OV threshold for

both Sections.

SCL/OS now becomes OS to program offset for the CORE

Section.

OPEN

3.3V

It sets

C address to 1100111.

OPEN

It sets

C address to 1100110 (default).

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