L6717ATR datasheet(38/57 Pages) STMICROELECTRONICS

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Output voltage positioning

L6717A

38/57

DocID024465 Rev 1

7.4

CORE section - analog offset (Optional - I2CDIS = 3.3 V)

When power manager I

C is disabled (I2CDIS = 3.3 V), L6717A still provide the way to add

positive/negative offset to the CORE section. In this particular conditions, the pin SCL/OS

becomes a virtual ground and allows programming a positive/negative offset (V

) for the

CORE section output voltage by connecting a resistor R

to SGND/VCC. The pin is

internally fixed at 1.240 V (2.0 V in case of negative offset, R

tied to VCC) so a current is

programmed by connecting the resistor R

between the pin and SGND/VCC: this current

is mirrored and then properly sunk/sourced from the FB pin as shown in

Figure 10. Output

voltage is then programmed as follow:

Offset resistor can be designed by considering the following relationship (R

is be fixed by

the droop effect):

(positive offset)

(negative offset)

Caution:

Offset implementation is optional, in case it is not desired, simply short the pin to GND.

Note:

In the above formulas, RFB has to be considered being the total resistance connected

between FB pin and the regulated voltage. kDRP has to be considered having its default

value since power manager I2C is disabled.

7.5

NB section - current reading

NB section performs the same differential current reading across DCR as the CORE

Section. According to

Section 7.2, the current that flows from the NB_CSN pin is then given

by the following equation (See

Figure 11):

G_NB

resistor is typically designed according to the OC threshold. See

Section 8.4 for

details.

7.6

NB section - defining load-line

This method introduces a dependence of the output voltage on the load current recovering

part of the drop due to the output capacitor ESR in the load transient. Introducing a

dependence of the output voltage on the load current, a static error, proportional to the

output current, causes the output voltage to vary according to the sensed current.

Figure 11 shows the current sense circuit used to implement the load-line. The current

flowing across the inductor DCR is read through R

G_NB

. R

G_NB

programs a trans-

conductance gain and generates a current I

DROOP_NB

proportional to the current delivered

by the NB section that is then sourced from the NB_FB pin with proper gain defined by the

DRP_ADJ command (k

DRPNB

). R

FB_NB

gives the final gain to program the desired load-line

CO R E

VID

DR P

DR O O P

⋅

–

()

⋅

–

1.240 V

------------------- R

⋅

VC C

2.0 V

–

-------------------------------- R

⋅

NB_CSN

DCR(NB)

G_NB

------------------------- I

⋅

DROOP_NB

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