L6717ATR datasheet(44/57 Pages) STMICROELECTRONICS

44 / 57 page

Output voltage monitoring and protections

L6717A

44/57

DocID024465 Rev 1

Figure 14. FB disconnection protection

8.3

PWRGOOD

It is an open-drain signal set free after the soft-start sequence has finished; it is the logic

AND between the internal CORE and NB PGOOD (or just the CORE PGOOD in PVI mode).

It is pulled low when the output voltage of one of the two sections drops 250 mV below the

programmed voltage. It is masked during on-the-fly VID transitions as well as when the

CORE section is set to OFF (from SVI bus) while the NB section is still operative.

8.4

Overcurrent

The Overcurrent threshold has to be programmed to a safe value, in order to be sure that

each section doesn't enter OC during normal operation of the device. This value must take

into consideration also the extra current needed during the OTF-VID Transition (I

OTF-VID

)

and the process spread and temperature variations of the sensing elements (Inductor DCR).

Moreover, since also the internal threshold spreads, the design has to consider the

minimum/maximum values of the threshold. Considering the reading method, the two

sections will show different behaviors in OC.

8.4.1

CORE section

L6717A performs two different OC protections for the CORE section: it monitors both the

total current and the per-phase current and allows to set an OC threshold for both.

–

Per-Phase OC.

Maximum information current per-phase (I

INFOx

) is internally limited to 35

μA. This

end-of-scale current (I

OC_TH

) is compared with the information current generated

for each phase (I

INFOx

). If the current information for the single phase exceed the

end-of-scale current (i.e. if I

INFOx

> I

OC_TH

), the device will turn-on the LS

MOSFET until the threshold is re-crossed (i.e. until I

INFOx

< I

OC_TH

). After 4

consecutive events, the IC latches with all the MOSFETs of all the sections OFF

(HiZ).

–

Total current OC.

ILIM pin allows to define a maximum total output current for the system (I

OC_TOT

LIM

current is sourced from the ILIM pin (not altered by DRP_ADJ command). By

connecting a resistor R

ILIM

to SGND, a load indicator with 2.5V (V

OC_TOT

) end-of-

scale can be implemented. When the voltage present at the ILIM pin crosses

CORE_REFERENCE

COMP

VSEN

FBG

To VDD_CORE

(Remote Sense)

from DAC...

CORE and NB SECTION - VSEN AND FBG DISCONNECTION

500mV

FBG DISCONNECTED

CS1-

600mV

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