SPC560P50L5 datasheet(57/112 Pages) STMICROELECTRONICS

57 / 112 page

SPC560P44Lx, SPC560P50Lx

Electrical characteristics

Doc ID 14723 Rev 9

57/112

3.5.2

General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:

Equation 1 TJ = TA + (RθJA * PD)

where:

= ambient temperature for the package (°C)

RθJA

= junction to ambient thermal resistance (°C/W)

= power dissipation in the package (W)

The junction to ambient thermal resistance is an industry standard value that provides a

quick and easy estimation of thermal performance. Unfortunately, there are two values in

Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC

specification for the specified package.

Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate

temperature is used for the case temperature. Reported value includes the thermal resistance of the

interface layer.

Thermal characterization parameter indicating the temperature difference between the board and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal

characterization parameter is written as Psi-JB.

Thermal characterization parameter indicating the temperature difference between the case and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal

characterization parameter is written as Psi-JC.

Table 13.

Thermal characteristics for 100-pin LQFP

Symbol

Parameter

Conditions

Typical value Unit

RθJA

Thermal resistance junction-to-ambient,

natural convection(1)

Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets

JEDEC specification for this package.

Single layer board—1s

47.3

°C/

Four layer board—2s2p

35.3

°C/

RθJB

Thermal resistance junction-to-board(2)

Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC

specification for the specified package.

Four layer board—2s2p

19.1

°C/

RθJCtop

Thermal resistance junction-to-case

(top)(3)

Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate

temperature is used for the case temperature. Reported value includes the thermal resistance of the

interface layer.

Single layer board—1s

9.7

°C/

ΨJB

Junction-to-board, natural convection(4)

Thermal characterization parameter indicating the temperature difference between the board and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal

characterization parameter is written as Psi-JB.

Operating conditions

19.1

°C/

ΨJC

Junction-to-case, natural convection(5)

Thermal characterization parameter indicating the temperature difference between the case and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal

characterization parameter is written as Psi-JC.

Operating conditions

0.8

°C/

SPC560P50L5 데이터시트(PDF) 57 Page - STMicroelectronics

SPC560P50L5 데이터시트(HTML) 57 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL