SPC560P50L5 datasheet(16/112 Pages) STMICROELECTRONICS

16 / 112 page

Introduction

SPC560P44Lx, SPC560P50Lx

16/112

Doc ID 14723 Rev 9

For high priority interrupt requests, the time from the assertion of the interrupt request from

the peripheral to when the processor is executing the interrupt service routine (ISR) has

been minimized. The INTC provides a unique vector for each interrupt request source for

quick determination of which ISR has to be executed. It also provides a wide number of

priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To

allow the appropriate priorities for each source of interrupt request, the priority of each

interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be

supported. The INTC supports the priority ceiling protocol (PCP) for coherent accesses. By

providing a modifiable priority mask, the priority can be raised temporarily so that all tasks

which share the same resource can not preempt each other.

The INTC provides the following features:

●

Unique 9-bit vector for each separate interrupt source

●

8 software triggerable interrupt sources

●

16 priority levels with fixed hardware arbitration within priority levels for each interrupt

source

●

Ability to modify the ISR or task priority: modifying the priority can be used to implement

the Priority Ceiling Protocol for accessing shared resources.

●

2 external high priority interrupts directly accessing the main core and I/O processor

(IOP) critical interrupt mechanism

1.5.7

System status and configuration module (SSCM)

The system status and configuration module (SSCM) provides central device functionality.

The SSCM includes these features:

●

System configuration and status

–

Memory sizes/status

–

Device mode and security status

–

Determine boot vector

–

Search code flash for bootable sector

–DMA status

●

Debug status port enable and selection

●

Bus and peripheral abort enable/disable

1.5.8

System clocks and clock generation

The following list summarizes the system clock and clock generation on the SPC560P44Lx,

SPC560P50Lx:

●

Lock detect circuitry continuously monitors lock status

●

Loss of clock (LOC) detection for PLL outputs

●

Programmable output clock divider (

÷1, ÷2, ÷4, ÷8)

●

FlexPWM module and eTimer module can run on an independent clock source

●

On-chip oscillator with automatic level control

●

Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency

trimming by user application

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