ST7FOXU0 datasheet(74/123 Pages) STMICROELECTRONICS

74 / 123 page

On-chip peripherals

ST7FOXU0

74/123

Bit 2 = OVF Overflow Flag.

This bit is set by hardware and cleared by software by reading the ATCSR register. It

indicates the transition of the counter from FFFh to ATR value.

0: No counter overflow occurred

1: Counter overflow occurred

Caution:

When set, the OVF bit stays high for 1 fCOUNTER cycle (up to 1ms depending on the clock

selection) after it has been cleared by software.

Bit 1 = OVFIE Overflow Interrupt Enable.

This bit is read/write by software and cleared by hardware after a reset.

0: OVF interrupt disabled

1: OVF interrupt enabled

Bit 0 = CMPIE Compare Interrupt Enable.

This bit is read/write by software and clear by hardware after a reset. It allows to mask

the interrupt generation when CMPF bit is set.

0: CMPF interrupt disabled

1: CMPF interrupt enabled

Counter register high (CNTRH)

Reset Value: 0000 0000 (00h)

Counter register low (CNTRL)

Reset value: 0000 0000 (00h)

Bits 15:12 = Reserved, must be kept cleared.

Bits 11:0 = CNTR[11:0] Counter Value.

This 12-bit register is read by software and cleared by hardware after a reset. The

counter is incremented continuously as soon as a counter clock is selected. To obtain

the 12-bit value, software should read the counter value in two consecutive read

operations. As there is no latch, it is recommended to read LSB first. In this case,

CNTRH can be incremented between the two read operations and to have an accurate

result when ftimer=fCPU, special care must be taken when CNTRL values close to FFh

are read.

When a counter overflow occurs, the counter restarts from the value specified in the

ATR register.

CN11

CN10

CN9

CN8

Read only

CN7

CN6

CN5

CN4

CN3

CN2

CN1

CN0

Read only

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