ST7FOXU0 datasheet(82/123 Pages) STMICROELECTRONICS

82 / 123 page

On-chip peripherals

ST7FOXU0

82/123

Bits 7:0 = D[9:2] MSB of Analog Converted Value

ADC Control/data register Low (ADCDRL)

Reset value: 0000 00xx (0xh)

Bits 7:4 = Reserved. Forced by hardware to 0.

Bit 3 = SLOW Slow mode bit

This bit is set and cleared by software. It is used together with the SPEED bit in the

ADCCSR register to configure the ADC clock speed as shown on the table below.

Bits 1:0 = D[1:0] LSB of Analog Converted value

0000

SLOW

Read/write

Table 29.

Configuring the ADC clock speed

fADC

(1)

The maximum allowed value of fADC is 4 MHz (see Section 12.10 on page 108)

SLOW

SPEED

fCPU/2

fCPU

fCPU/4

Table 30.

ADC register mapping and reset values

Address

(Hex.)

label

0036h

ADCCSR

Reset Value

EOC

SPEED

ADON

CH2

CH1

CH0

0037h

ADCDRH

Reset Value

0038h

ADCDRL

Reset Value

SLOW

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