ST10F296 datasheet(191/346 Pages) STMICROELECTRONICS

191 / 346 page

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ST10F296E

I2C interface

191/346

I2C interface

The integrated I2C bus module handles the transmission and reception of frames over the

two-line SDA/SCL in accordance with the I2C bus specification. The I2C module can operate

in slave mode, in master mode or in multi-master mode. It can receive and transmit data

using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 kbit/sec (both

standard and fast I2C bus modes are supported).

The module can generate three different types of interrupt:

●

Requests related to bus events, such as start or stop events, arbitration lost, etc.

●

Requests related to data transmission

●

Requests related to data reception

These requests are issued to the interrupt controller by three different lines, and identified as

error, transmit, and receive interrupt lines.

When the I2C module is enabled by setting the XI2CEN bit in the XPERCON register, pins

P4.4 and P4.7 (SCL and SDA respectively mapped as alternate functions) are automatically

configured as bidirectional open-drain. The value of the external pull-up resistor depends on

the application. P4, DP4 and ODP4 cannot influence the pin configuration.

When the I2C cell is disabled (clearing the XI2CEN bit), pins P4.4 and P4.7 are standard I/O

controlled by P4, DP4 and ODP4.

16.1

I2C bus speed selection

The speed of the I2C interface may be selected between standard mode (0-100 kHz) and

fast I2C mode (100-400 kHz). The selection is provided through the FM/SM bit in the clock

control register 1 (CCR1).

Once bus mode is selected, the frequency of the serial clock line can be defined by setting

prescaler bits CC0 to CC11 (CCR1 and CCR2). Different formulae are used according to the

mode selected:

●

Standard mode (FM/SM = 0): FSCL ≤100 kHz

●

Fast mode (FM/SM = 1): FSCL > 100 kHz

SCL

CPU

CC11

…CC0

[] 7

()

⁄

SCL

CPU

CC11

…CC0

[] 9

()

⁄

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ST10F296 데이터시트(PDF) 191 Page - STMicroelectronics

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