ST10F296 datasheet(247/346 Pages) STMICROELECTRONICS

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ST10F296E

Programmable output clock divider

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Programmable output clock divider

A specific register mapped on the XBus allows the division factor on the CLKOUT signal

(P3.15) to be chosen. This register, XCLKOUTDIV, is mapped on the XMiscellaneous

memory address range.

XCLKOUTDICV register

The CPU clock is output on P3.15, by default, when the CLKOUT function is enabled

(setting the CLKEN bit of the SYSCON register).

By setting the XMISCEN and XPEN bits of the XPERCON and SYSCON registers

respectively, the clock prescaling factor can be programmed. In this way, a prescaled value

of the CPU clock can be output on P3.15.

When the CLKOUT function is not enabled (clearing the CLKEN bit of the SYSCON on

P3.15), P3.15 does not output a clock signal, even though the XCLKOUTDIV register is

programmed.

XCLKOUTDIV (EB02h)

XBus

Reset value: --00h

987

65432

---

-----

DIV

---

-----

Table 136.

XCLKOUTDIV register description

Bit

Bit name

Function

7-0

DIV

Clock divider setting

00h: FCLKOUT = FCPU/DIV+1

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ST10F296 데이터시트(PDF) 247 Page - STMicroelectronics

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