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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST10F296 데이터시트(PDF) 243 Page - STMicroelectronics |
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ST10F296 데이터시트(HTML) 243 Page - STMicroelectronics |
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243 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E Power reduction modes 243/346 Figure 94. Simplified power-down exit circuitry 1. Legend: exit_pwrd = exit power-down internal signal en_clk_n = clock enable signal (negated: active low) Figure 95. Power-down exit sequence when using an external interrupt (PLL x 2) Enter External interrupt Reset Stop PLL Stop oscillator VDD DQ Q cd System clock CPU and peripheral clocks RPD VDD exit_pwrd en_clk_n Pull-up Weak pull-down (~ 200 µA) power-down Q2 VDD DQ Q cd Q1 CPU clk Power-down signal External RPD exit_pwrd XTAL1 (internal) interrupt (internal) Delay for oscillator/PLL stabilization ~ 2.5 V Obsolete Product(s) - Obsolete Product(s) |
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