ST10F296 datasheet(303/346 Pages) STMICROELECTRONICS

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ST10F296E

Electrical characteristics

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24.7.1

Conversion timing control

When a conversion starts, the capacitances of the converter are first loaded via the

respective analog input pin to the current analog input voltage. The time to load the

capacitances is referred to as the sample time. Next, the sampled voltage is converted into a

digital value in several successive steps which corresponds to the 10-bit resolution of the

ADC. During these steps the internal capacitances are repeatedly charged and discharged

via the VAREF pin.

The current that must be drawn from the sources for sampling and changing charges

depends on the duration of each step because the capacitors must reach their final voltage

level as close to the given time as possible. However, the maximum current that a source

can deliver depends on its internal resistance.

The amount of time that sampling and converting takes during conversion can be

programmed within a certain range in the ST10F296E relative to the CPU clock. The

absolute time consumed by the different conversion steps is therefore independent from the

general speed of the controller. This allows the device ADC to be adjusted to the properties

of the system.

Fast conversion can be achieved by programming the respective times to their absolute

possible minimum. This is preferable for scanning high frequency signals. However, the

internal resistance of the analog source and analog supply must be sufficiently low.

High internal resistance can be achieved by programming the respective times to a higher

value or to their possible maximum. This is preferable when using analog sources and

supplies with a high internal resistance to keep the current as low as possible. However, the

conversion rate in this case may be considerably lower.

The conversion times are programmed via the upper four bits of the ADCON register. Bit

fields ADCTC and ADSTC define the basic conversion time and in particular the partition

between the sample phase and comparison phases. Table 167 lists the possible

combinations. The timings refer to the unit TCL, where fCPU = 1/2 TCL. A complete

conversion time includes the conversion itself, the sample time and the time required to

transfer the digital value to the result register.

DNL, INL, OFS and TUE are tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 5.0 V. They are guaranteed by

design characterization for all other voltages within the defined voltage range. ‘LSB’ has a value of

VAREF/1024. The specified TUE (±2 LSB) is also guaranteed with an overload condition (see IOV

specification) occurring on a maximum of two unselected analog input pins if the absolute sum of input

overload currents on all analog input pins does not exceed 10 mA.

The coupling factor is measured on a channel while the overload condition occurs on the adjacent

unselected channels with the overload current within the different specified ranges (for both positive and

negative injection current).

Refer to Figure 99

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