ST10F296 datasheet(301/346 Pages) STMICROELECTRONICS

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Electrical characteristics

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Erase suspend latency(7)

-30

µs

Erase suspend request rate(7)

Min delay between two

requests

Set protection(7)

170

µs

Values are after about 100 cycles due to testing routines (0 cycles for the final customer).

The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values

are characterized but not guaranteed.

Word and double word programming times are provided as average values derived from a full sector programming time.

The absolute value of a word or double word programming time may be longer than the provided average value.

Bank erase is obtained through a multiple sector erase operation (setting bits related to all sectors of the bank).

Module erase is obtained through a sequence of two bank erase operations (since each module is composed of two

banks).

Chip erase is obtained through a sequence of two module erase operations on the Imodule and Xmodule.

Not 100% tested, guaranteed by design characterization.

Table 164.

Flash characteristics (continued)

Parameter

Typical

TA = 25 °C

Maximum

TA = 125 °C

Unit

Notes

0 cycles(1)

100 k cycles(2)

Table 165.

Data retention characteristics

Number of program/erase cycles

(-40 °C

≤TA ≤125 °C)

Data retention time

(average ambient temperature 60 °C)

832 Kbyte

(code store)

64 Kbyte

(EEPROM emulation)(1)

Two 64 Kbyte Flash sectors may be typically used to emulate up to 4, 8, or 16 Kbytes of EEPROM.

Therefore, in case of an emulation of a 16 Kbyte EEPROM, 100 000 Flash program/erase cycles are

equivalent to 800 000 EEPROM program/erase cycles. For an efficient use of the read while write feature

and/or EEPROM emulation, please refer to the dedicated application note (AN2061, EEPROM Emulation

with ST10F2xx) on www.st.com.

0 - 100

> 20 years

1,000

> 20 years

10,000

10 years

100,000

1 year

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