ST10F296 datasheet(317/346 Pages) STMICROELECTRONICS

317 / 346 page

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296E

Electrical characteristics

317/346

24.8.9

PLL jitter

Two kinds of PLL jitter are defined:

Self referred single period jitter

Also called ‘period jitter’. It can be defined as the difference between the Tmax and Tmin,

where Tmax is the maximum time period of the PLL output clock and Tmin is the minimum

time period of the PLL output clock.

Self referred long term jitter

Also called ‘N period jitter’. It can be defined as the difference of Tmax and Tmin, where Tmax

is the maximum time difference between N + 1 clock rising edges and Tmin is the minimum

time difference between N + 1 clock rising edges. N should be kept sufficiently large to have

obtain long term jitter. N = 1 becomes the single period jitter.

Jitter at the PLL output is caused by:

●

Jitter in the input clock

●

Noise in the PLL loop

24.8.10

Jitter in the input clock

The PLL acts as a low pass filter for any jitter in the input clock. Input clock jitter, with the

frequencies within the PLL loop bandwidth, is passed to the PLL output and higher

frequency jitter (frequency > PLL bandwidth) is attenuated at 20 dB/decade.

24.8.11

Noise in the PLL loop

Noise is attributed to the following sources:

●

Device noise of the circuit in the PLL

●

Noise in the supply and substrate

Device noise of the circuit in the PLL

Long term jitter is inversely proportional to the bandwidth of the PLL. The wider the loop

bandwidth, the lower the jitter, due to noise in the loop. Moreover, long term jitter is

practically independent of the multiplication factor.

The most noise sensitive circuit in the PLL is the VCO. There are two main sources of noise:

Thermal (random and frequency independent noise) and flicker (low frequency noise, 1/f).

For the frequency characteristics of the VCO circuitry, the effect of the thermal noise results

in a 1/f2 region in the output noise spectrum, while the flicker noise results in 1/f3. Assuming

a noiseless PLL input and supposing that the VCO is dominated by its 1/f2 noise, the root

mean square value of the accumulated jitter is proportional to the square root of N, where N

is the number of clock periods within the considered time interval.

On the contrary, assuming a noiseless PLL input and supposing that the VCO is dominated

by its 1/f3 noise, the RMS value of the accumulated jitter is proportional to N, where N is the

number of clock periods within the considered time interval.

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296 데이터시트(PDF) 317 Page - STMicroelectronics

ST10F296 데이터시트(HTML) 317 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL