ST10F296 datasheet(314/346 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F296E

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The limits on input frequency are 4-12 MHz since use of the internal oscillator amplifier is

required. When the PLL is not used and the CPU clock corresponds to FXTAL/2, an external

crystal or resonator must be used. It is not possible to force any clock though an external

clock source.

24.8.4

Prescaler operation

When pins P0.15-13 (P0H.7-5) equal 001 during reset, the CPU clock is derived from the

internal oscillator (input clock signal) by a 2:1 prescaler.

The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU

(duration of an individual TCL) is defined by the period of the input clock fXTAL.

The timings listed in this section that refer to TCL can be calculated using the fXTAL period

for any TCL.

If the OWDDIS bit in the SYSCON register is cleared, the PLL runs on its free-running

frequency and delivers the clock signal for the oscillator watchdog. If the OWDDIS bit is set,

the PLL is switched off.

24.8.5

Direct drive

When pins P0.15-13 (P0H.7-5) equal 011 during reset, the on-chip PLL is disabled, the on-

chip oscillator amplifier is bypassed and the CPU clock is directly driven by the input clock

signal on the XTAL1 pin.

The frequency of the CPU clock (fCPU) directly follows the frequency of fXTAL, so, the high

and low time of fCPU (duration of an individual TCL) is defined by the duty cycle of the input

clock fXTAL.

Therefore, the timings given in this section refer to the minimum TCL. This minimum value

can be calculated using Equation 43.

Equation 43

Where DC = Duty cycle.

For two consecutive TCLs, the deviation caused by the duty cycle of fXTAL is compensated,

so, the duration of 2TCL is always 1/fXTAL.

The minimum value, TCLmin, is used only once for timings that require an odd number of

TCLs (1, 3, ...). Timings that require an even number of TCLs (2, 4, ...) may use Equation

44.

Equation 44

The address float timings in multiplexed bus mode (t11 and t45) use the maximum duration of

TCL (TCLmax = 1/fXTAL x DCmax) instead of TCLmin.

If the OWDDIS bit in the SYSCON register is cleared, the PLL runs on its free-running

frequency and delivers the clock signal for the oscillator watchdog. If the OWDDIS bit is set,

the PLL is switched off.

TCL

min

XTAL

min

⁄

2TCL

XTAL

⁄

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