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DSM2190F4V 데이터시트(PDF) 47 Page - STMicroelectronics |
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DSM2190F4V 데이터시트(HTML) 47 Page - STMicroelectronics |
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47 / 61 page ![]() 47/61 DSM2190F4 Table 27. CPLD Combinatorial Timing Note: 1. Fast Slew Rate output available on PB3-PB0, and PD2-PD0. Symbol Parameter Conditions -15 PT Aloc Turbo Off Slew Rate1 Unit Min Max tPD CPLD Input Pin/Feedback to CPLD Combinatorial Output 45 Add 4 Add 20 Sub 6 ns tEA CPLD Input to CPLD Output Enable 45 Add 20 Sub 6 ns tER CPLD Input to CPLD Output Disable 45 Add 20 Sub 6 ns tARP CPLD Register Clear or Preset Delay 43 Add 20 Sub 6 ns tARPW CPLD Register Clear or Preset Pulse Width 30 Add 20 ns tARD CPLD Array Delay Any Macrocell 29 Add 4 ns |
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