L9634

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Figure 11. Serial Mode: Deployment Sequence with Pulse Stretch Timer Enabled

Figure 12. Serial Mode: Deployment Sequence with Pulse Stretch Timer Disabled

4.4

ARM01 / ARMIN

In discrete mode, this pin acts as the ARM input channel 0 and channel 1. In serial mode, this pin acts as

the input of Arming shift register.

The ARMIN input takes data from the processor or another OSD while ARMEN is asserted. The MSB is

the first bit of each word received on ARMIN. The LSB is the last bit of each word received on ARMIN.

See Figure 8 below for Aming shift register. This pin has a TTL level compatible input voltages allowing

proper operation with another devices using a 3.3V to 5.0V supply.

t

PULSE

Pulse Stretch Timer

2 ms

or 4ms

Deploy

Valid Deployment Window

SPI CS

Deploy Success Flag

1: SPI Deploy Command

2: Clear Deploy Success Flag

SPI CS Notes:

1

1

2

t

PULSE

2 ms

or 4ms

t

PULSE

Valid

Deployment

Window

1

1

2

Valid

Deployment

Window

t < t

PULSE

Valid Deployment Window

t

PULSE

1

3

3: SPI Idle Command

t

PULSE

3

ARMx Status Flag

ARMEN

A

B

A

B

A

B

A

B

A

B

ARMEN Notes:

A: Arming Enable

B: Arming Disable

DEPEN input is assumed to be active in this sequence.

De-glitch

Deploy Status Flag

t

PULSE

t

PULSE

Obsolete

Product(s)

- Obsolete

Product(s)