L9634

20/36

4.16 High Side MOS Diagnostic

Upon detection of the following conditions, OSD turns the high side driver off and terminate the diagnostic

Any of the above conditions are considered as a normal operation. Upon detection any of these conditions,

OSD does not set the high side driver fault bits.

20 for MOS test diagram.

4.17 Loss of Ground Diagnostic

Loss of ground is detected when the power ground of a deployment loop has a high impedance/open con-

nection to the ground. Each channel has a dedicated power ground and a dedicated loss of ground detec-

tion. Upon a detection of loss of ground condition, OSD inhibits a diagnostic and a deployment for the

respective channel. The rest of the channels are not affected by a loss of ground condition on the other

channels. A loss of ground condition does not affect a deployment or a pulse strech timer that is already

started.

A ground reference for OSD logic is connected to GND0 pin. When OSD detects a high impedance on this

ground reference, OSD will go in reset mode.

4.18 Serial Peripheral Interface (SPI)

The OSD contains a serial peripheral interface consisting of Serial Clock (SCLK), Serial Data Out (MISO),

Serial Data In (MOSI), and Chip Select (CS). This device is configured as an SPI slave.

Figure 21. SPI Block Diagram

4.19 Chip Select (CS)

The CS input selects OSD for serial data transfers. This TTL-compatible input has an internal pull-down

to command the de-asserted state should an open circuit condition occur When CS is asserted, the MISO

pin is released from tri-state mode, and all status information is latched in the SPI shift register. While CS

is asserted, register data is shifted in the MOSI pin and shifted out the MISO pin on each subsequent

SCLK. When CS is negated, the MISO pin is tri-stated and the fault register reloaded (latched) with the

current filtered status data.

must also be immune to spurious pulses as defined in the SPI Timing table (MISO may come out of tri-

state, but no status bits can be cleared and no control bits altered). Glitches on the CS line while SCLK is

not running will be ignored, although the MISO pin may be enabled. In each valid CS, OSD allows 16-bit

MISO

MSB

LSB

Control Bits

Status Bits

Input Shift Register

SCLK

MOSI

CS

Output Shift Register

cs

vdd

vss

30

µA

Obsolete

Product(s)

- Obsolete

Product(s)