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L9634

4.35 MISO Bit Definition

Figure 23. MISO Bit Layout

Table 27. MISO Mode Bits Definition

4.36 Register Mode Response

Register Mode Response is defined as shown in table.

Table 28. MISO Register Mode Response Definition

Bit D13 is used to reflect the status of MOSI Read/Write bit (refer to bit D13 in "MOSI Register Mode Mes-

sage Definition table").

Bit D7 through bit D0 contain data bits. These data bits contain either diagnostic fault register or ADC re-

sistance measurement register depending upon the MOSI request. Both register are defined as shown in

"Diagnostic Fault Register Channel 0 and 1 table" and "ADC Resistance Measurement Register table".

Bit D15

Bit D14

Description

0

0

Register Mode Response

0

1

Command Mode Response

1

0

SPI Fault Response

1

1

Status Response

Bit

State

Description

D15

0

Mode Bits

D14

0

D13

Echo of MOSI Read/Write Bit

D12

Address Bits

Refer to Address-bit Definition table

D11

D10

D9

D8

D7

Data Bits

D6

D5

D4

D3

D2

D1

D0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

MSB

LSB

Obsolete

Product(s)

- Obsolete

Product(s)