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4.27 Deployment Configuration Register 1

The deployment configuration register 1 is defined as shown in the next table. During a deployment event,

a write request to this register is inhibited.

Table 15. Deployment Configuration Register 1

Bit D3 through bit D0 is used to inhibit the ARMx signal from initiating the pulse stretch timer. When these

bits are "0," ARMx signal is prohibited from initiating the timer. Otherwise, a valid ARMx signal starts the

timer. If the timer has already initiated by the SPI deployment command, the ARMx signal does not affect

the timer.

Bit D7 and bit D6 is used to set the period of pulse stretch timer. OSD has 8 independent timers for each

channel. Either a valid ARMx or a SPI deployment command is capable to start the pulse stretch timer.

These bits set the timer duration according to table. These values are default to %00 after battery connect.

Table 16. Pulse Stretch Timer

Bit

Status

Description

D7

Pulse Stretch timer (see table)

D6

D5

0

ARM Parallel Mode (default)

1

ARM Serial Mode

D4

-

Don’t Care

D3

0

ARM67 Pulse Stretch Disable (default)

1

ARM67 Pulse Stretch Enable

D2

0

ARM45 Pulse Stretch Disable (default)

1

ARM45 Pulse Stretch Enable

D1

0

ARM23 Pulse Stretch Disable (default)

1

ARM23 Pulse Stretch Enable

D0

0

ARM01 Pulse Stretch Disable (default)

1

ARM01 Pulse Stretch Enable

Bit D7

Bit D6

Stretch Period (ms)

00

7.5

01

15

10

30

11

60

Obsolete

Product(s)

- Obsolete

Product(s)