MC68HC908AP16CFB datasheet(67/440 Pages) MOTOROLA

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Configuration & Mask Option Registers (CONFIG & MOR)

Configuration Register 1 (CONFIG1)

MC68HC908AP Family — Rev. 2.5

Data Sheet

MOTOROLA

The mask option register (MOR) is used for selecting one of the three

clock options for the MCU. The MOR is a byte located in FLASH

memory, and is written to by a FLASH programming routine.

5.3 Configuration Register 1 (CONFIG1)

COPRS — COP Rate Select Bit

COPRS selects the COP time out period. Reset clears COPRS. (See

Section 21. Computer Operating Properly (COP).)

1 = COP time out period = 213 – 24 ICLK cycles

0 = COP time out period = 218 – 24 ICLK cycles

LVISTOP — LVI Enable in Stop Mode Bit

When the LVIPWRD or LVIREGD bit is clear, setting the LVISTOP bit

enables the LVI to operate during stop mode. Reset clears LVISTOP.

(See Section 22. Low-Voltage Inhibit (LVI).)

1 = LVI enabled during stop mode

0 = LVI disabled during stop mode

NOTE:

If LVISTOP=0, set LVIRSTD=1 before entering stop mode.

LVIRSTD — LVI Reset Disable Bit

LVIRSTD disables the reset signal from the LVI module. (See

Section 22. Low-Voltage Inhibit (LVI).)

1 = LVI module resets disabled

0 = LVI module resets enabled

Address:

$001F

Bit 7

654321

Bit 0

Read:

COPRS

LVISTOP LVIRSTD LVIPWRD LVIREGD

SSREC

STOP

COPD

Write:

Reset:

00000000

Figure 5-2. Configuration Register 1 (CONFIG1)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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