STV3550 datasheet(65/144 Pages) STMICROELECTRONICS

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STV3550

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5.4.7

Data Clock Output

We could output the block clock with a choice of polarity and four different delays according to the

configuration register.

We could also select an output of the original clock frequency or the clock frequency divided by 2.

5.4.8

Pad Control

If a PAD is not used by the Video application a way to control its state is provided using software.

One bit register control if the PAD is in video mode or in software mode, another bit register controls

the software level for the PAD.

The PAD stays in push pull output in both cases. The software state is available only on the next

edge of the clk_dac clock. The clk_dac clock must be enabled to change the PAD state.

We are able to reconfigure the following PAD:

P_video<12:29>

dvo_de

Vsync

dvo_clk_2162

The user must take care of the consistency choice of the Digital Video Output Interface.

5.4.9

We have a dedicated register interface (STbus T1).

Address

Description

0x18

Pad output

0x14

Pad Control

0x10

DE Vertical control

0x0C

DE Horizontal control

0x08

Vsync control

0x04

Hsync control

0x00

block control

Dclk

clk_dac

sel_delay

sel_pol

sel_divclk

delay

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