STV3550 datasheet(70/144 Pages) STMICROELECTRONICS

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STV3550

CPU and System Management Functional Description

Write operations in Flash require specific sequences on the data and address buses. Since the

STV3550 can drive any data and any addresses on the buses, write operations into Flash can be

performed if the Flash device is used as an asynchronous memory.

Control signals such as chip select, write enable and output enable (active low) can be configured

by software, so that they are asserted or not by the STV3550 Memory Interface during each

operation.

6.3.8.2 Flash Requirements

Time is expressed in number of STV3550 system clock cycles. Phase refers to half a cycle.

●

Flash size up to 16 Mbits

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Access Cycle Time from 2 to 127 cycles (tAC)

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Bus Release Time from 0 to 15 cycles (tBR)

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Data Drive Delay from 0 to 31 phases after start of Access Cycle (tDD)

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Falling edge of NOT_CS_FLASH from 0 to 15 phases or cycles after start of Read Access

Cycle (tCSr1)

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Rising edge of NOT_CS_FLASH from 0 to 15 phases or cycles before end of Read Access

Cycle (tCSr2)

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Falling edge of NOT_CS_FLASH from 0 to 15 phases or cycles after start of Write Access

Cycle (tCSw1)

●

Rising edge of NOT_CS_FLASH from 0 to 15 phases or cycles before end of Write Access

Cycle (tCSw2)

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Falling edge of NOT_CAS (NOT_OE) from 0 to 15 phases or cycles after start of Read Access

Cycle (tOE1)

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Rising edge of NOT_CAS (NOT_OE) from 0 to 15 phases or cycles before end of Read

Access Cycle (tOE2)

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Falling edge of RD_NOT_WR from 0 to 15 phases or cycles after start of Write Access Cycle

(tWE1)

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Rising edge of RD_NOT_WR from 0 to 15 phases or cycles before end of Write Access Cycle

(tWE2)

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Latch Point from 0 to 15 cycles before end of Access Cycle (tLP)

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