STV3550 datasheet(66/144 Pages) STMICROELECTRONICS

66 / 144 page

66/144

STV3550

CPU and System Management Functional Description

6.1

ST20 C2C200 CPU Core

6.1.1

General Information

This is the 32-bit ST20 C2C200 CPU core from the ST20 CPU family with a programmable

operating frequency between 4 MHz and 100 MHz, depending on the operating mode (full speed or

low power). The cell includes a 4-kB instruction cache memory, a 4-kB data cache memory, a 8-kB

SRAM, a Diagnostic Controller Unit (DCU) and an Interrupt Controller (ITC).

6.1.2

Main Features

●

32-bit VL-RISC Processor

●

60 MIPS (Dhrystone 2.1) at 100 MHz clock

●

16 cache registers of 32-bits providing fast access to local variables

●

Fast-context switch time (less than 1 µs)

●

Up to 16 interrupt inputs

●

Includes 4-kB instruction cache memory, 4-kB data cache memory, and 8-kB SRAM for DMA

transactions or cache increase

●

Includes a Diagnostic Controller Unit for Real Time Debugging via a JTAG port and ST20

emulator

6.2

ST Bus Interconnect Overview

The STV3550 Interconnect is based on the STBus architecture. Its main function is to allow data to

flow between different blocks called “initiators” and “targets”. Each initiator can make a transaction

with any target. The priority of the transaction depends on the arbitration made by each interconnect

module or arbiter.

6.3

STV3550 Memory Interface

In the STV3550, the memory interface is in four parts:

1. The External Memory Interface (EMI) manages all memory accesses from a protocol point of

view.

2. The Pad Glue Logic (PGL) is used for multiplexing and sharing functions on the memory pads

in order to optimize the number of pins. The Pad Glue Logic mainly implements combinational

logic as well as some control logic.

3. The Pad Logic (PL) solves timing issues encountered when connecting high speed devices on

a printed circuit board (PCB). The Pad Logic mainly implements the bi-directional pad and its

associated control logic to accommodate the setup and hold time of memory devices.

4. The Delay Locked Line (DLL)

6.3.1

Memory Devices

The STV3550 requires a ROM device that contains the application software and a RAM device for

video and software data. If the ROM bandwidth is not sufficient, the application software may be

downloaded from ROM to RAM when booting the STV3550. (The download operation is

implemented in software.)

STV3550 데이터시트(PDF) 66 Page - STMicroelectronics

STV3550 데이터시트(HTML) 66 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL