STV3550 datasheet(135/144 Pages) STMICROELECTRONICS

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Electrical Characteristics

STV3550

135/144

9.8

I²C Bus Characteristics

Table 27: Key I²C Timing Requirements

Parameter

Min.

Max.

SCL Clock Frequency

100 kHZ or 400 kHz1

1. In FAST Mode

Hold Time of SCL after SDA START or REPSTART Condition.

After this time the first clock low pulse is created

1.0us or 0.6us

LOW Period of the SCL clock

4.7us or 1.3us

HIGH period of the SCL clock

4.0us or 0.6us

SDA Set-up time relative to SCL for a repeated START condition

4.6us or 0.6us

SDA Data Hold Time relative to SCL

300ns2

2. Actual requirement is 0ns but hold time must be at least 300ns on SDA line to comply with uncertain period of max fall

time of 300ns on the SCL line.

SDA Data Setup Time relative to SCL

250ns or 100ns3

3. In FAST mode, but when used with normal mode devices must still meet the 250ns minimum

Rise time of SDA and SCL lines

20+0.1Cb

4. Where Cb is the total capacitance on one bus line in pF

100ns or 300ns

Fall time of SDA and SCL lines

20+0.1Cb

300ns

SDA Setup time relative to SCL for a STOP condition

4.0us or 0.6us

Capacitive load of each bus line (Cb)

400pF

Table 28: I²C Timing Constants

I²C Timing Name

I²C Standard

Minimum Time

Constant Value

(cycles)

Typical at

60 MHz

Data Hold Time

300ns

350ns

Setup Time For STOP Condition TSU.STO

4.0us

300

5.0us

Setup Time For START (repeated) Condition TSU.ST

4.7us

300

5.0us

Hold Time (repeated) START Condition THD:STA

4.0us

300

5.0us

Data Setup Time TSU:DAT

250ns

300ns

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