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SLG46721 데이터시트(PDF) 80 Page - Dialog Semiconductor

부품명 SLG46721
상세설명  Logic & Mixed Signal Circuits
PDF  101 Pages
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SLG46721
19.2.2 Power Down
During powerdown, macrocells in SLG46721 are powered off and logic macrocells may switch states after falling below 1.4 V.
The I/O buffers are disabled when POR goes low at VDD~1 V. Please note that during a slow rampdown, outputs can possibly
switch state during this time.
Figure 42. Power Down
Outputs can possibly switch state during this time
VDD (V)
Time
1.6 V
1.15 V
2 V
1 V
1 V VREF Out Signal



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