CS8952 datasheet(61/82 Pages) CIRRUS

61 / 82 page

CS8952

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

6.19

10BASE-T Status Register - Address 1Bh

Reserved

Polarity OK

10BASE-T

Serial

Reserved

765

4321

Reserved

BIT

NAME

TYPE

RESET

DESCRIPTION

15:11 Reserved

Read Only

0 0000

Polarity OK

Read Only

When high, the polarity of the receive signal (at the

RXD+/RXD- inputs) is correct. If clear, the polarity is

reversed. If the Polarity Disable bit of 10BASE-T

Configuration Register (address 1Ch) is clear, then

the polarity is automatically corrected, if needed. The

Polarity OK status bit shows the true state of the

incoming polarity independent of the Polarity Disable

bit.

10BASE-T Serial

Read/Write Reset to the value

on the 10BT_SER

pin.

When set, this bit selects 10BASE-T serial mode.

When low, this bit selects 10BASE-T nibble mode.

This bit will only affect the CS8952 if it has been con-

figured for 10 Mb/s operation.

8:0

Reserved

Read Only

0 0000 0000

CS8952 데이터시트(PDF) 61 Page - Cirrus Logic

CS8952 데이터시트(HTML) 61 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

데이터시트 다운로드

링크 URL