DSP56857 datasheet(313/662 Pages) FREESCALE

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Functional Description

Enhanced Synchronous Serial Interface (ESSI), Rev. 4

Freescale Semiconductor

12-13

Figure 12-3 and Table 12-7 describes the functions performed during receive operation in this

mode.

Figure 12-3. Normal Mode Receive Timing (WL=8 bit words, DC=1)

Table 12-7.

Normal Mode Receive Operations

Step

TXFIFO Disabled1

See Figure 12-2.

TXFIFO Enabled

Leading edge of frame sync occurs on the SC1

pin.

——

Falling edge of receive clock occurs on the SC0

pin and the next bit of data is shifted into the

RXSR register.

——

When WL bits2 have been received. RXSR

contents are transferred to the SRX register on

the next falling edge of the receive clock. The

SRX register is actually loaded during the middle

of the last receive bit.

See Section 12.8.11.

——

Flag status update

The RDR bit is set

The RFF bit is set if the level of data in

the RSFIFO rises above the

watermark level.

If the RIE bit is set, enabling receive interrupts,

then: Other options for processing the data

transfer is either polling or DMA transfers.

—

Receive interrupt occurs when RFF is

set.

Receive overrun (setting the ROE bit of the SSR

Section 12.8.11 describes what happens when the ROE bit is set.

—

Data is read from the SRX before the

RXSR tries to provide more data to a

full RSFIFO. It can take several frame

times to fill the RXFIFO.

Repeat at set 1 on the next frame sync.4

The frame sync must not occur earlier than it is configured in the STXCR as documented in Section 12.8.11.

——

SC0

SC1

SRD

RXSR Register

SRX Register

RDR Status Bit / Interrupt

Valid

Indefinite transition depends on SW interrupt processing

Invalid

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