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DSP56857 데이터시트(PDF) 329 Page - Freescale Semiconductor, Inc

부품명 DSP56857
상세설명  Digitial Signal Controller
PDF  662 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 데이터시트(HTML) 329 Page - Freescale Semiconductor, Inc

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Register Descriptions (ESSI0_BASE = $1FFE20, ESSI1_BASE = $1FFE00)
Enhanced Synchronous Serial Interface (ESSI), Rev. 4
Freescale Semiconductor
12-29
Figure 12-16. Transmit Data Path (TSHFD = 1)
12.8.4 ESSI Receive Register (SRX)
The SRX is a 16-bit, read-only register. It always accepts data from the Receive Shift Register
(RXSR) as it becomes full. The data read occupies the most significant portion of the SRX
register. The unused bits (least significant portion) are read as 0s.
If the Receive Data Full Interrupt is enabled, the interrupt is asserted whenever the SRX register
becomes full. When the Receive FIFO is also enabled, the Receive FIFO must be above its
watermark before the interrupt is asserted.
Figure 12-17. ESSI Receive Data Register (SRX)
See Programmer’s Sheet on Appendix page B - 69
12.8.5 ESSI Receive FIFO Register (RXFIFO)
The RXFIFO is a 8
× 16-bit FIFO register used to buffer samples received in the ESSI Receive
Data Shift Register (RXSR). The receive FIFO is enabled by setting the RFEN bit of the SCR3
Control Register.
Received data is then held in the FIFO if the data in the SRX has not yet been read.
Base + $3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
HIGH BYTE
LOW BYTE
Write
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STX
15
0
ESSI
87
15
0
TXSR
8
7
6
5
4
8 bits
10 bits
12 bits
16 bits
16 bits
8 bits
12 bits
10 bits



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