DSP56857 datasheet(341/662 Pages) FREESCALE

341 / 662 page

Enhanced Synchronous Serial Interface (ESSI), Rev. 4

Freescale Semiconductor

12-41

12.8.8.7 Transmit Enable 2 (TE2)—Bit 10

This control bit enables the transfer of the contents of the STX2 register to its Transmit Data Shift

ignored when the ESSI is in the Asynchronous mode.

•

0 = The transmitter continues to send the data currently in TXSR2, then disables the

transmitter. The serial output is tri-stated and any data present in the STX2 register is not

transmitted; that is to say, data can be written to the STX2 register with the TE2 and TDE

bits cleared, but data is not transferred to the TXSR2.

•

1 = On the next frame boundary, the transmit 2 portion of the ESSI is enabled for that

frame. With internally generated clocks, the frame boundary will occur within a word

time. If the TE2 bit is cleared, then set again during the same transmitted word, the data

continues to be transmitted. If the TE2 bit is set again during a different time slot, data is

not transmitted until the next frame boundary.

When the TE2 bit remains clear until the start of the next frame, it causes the SC1 signal to act as

a serial I/O flag from the start of the frame in both Normal and Network modes.

The Normal Transmit Enable sequence is to write data to the STX2 register or to the STSR before

setting the TE2 bit. The Normal Transmit Disable sequence is to clear the TE2 bit and the TIE bit

after the TDE bit is set. This bit should be cleared when clearing ESSIEN.

Note:

Setting the TE2 bit does not affect the generation of frame sync or output flags.

12.8.8.8 Reserved—Bits 9–8

These bits are reserved or not implemented. They cannot be read nor modified by writing.

12.8.8.9 Synchronous Mode (SYN)—Bit 7

This control bit enables the Synchronous mode of operation. In this mode, the transmit and

receive sections share a common clock pin (SCK) and frame sync pin (SC2). Table 12-3

illustrates the clock configuration options. Table 12-4 illustrates the frame sync options.

Note:

Synchronous mode operation with all transmitters disabled and the receiver enabled

requires an externally generated frame sync.

12.8.8.10 Transmit Shift Direction (TSHFD)—Bit 6

This bit controls whether the MSB or LSB is transmitted first for the transmit section.

•

0 = MSB is transmitted first.

•

1 = LSB is transmitted first.

DSP56857 데이터시트(PDF) 341 Page - Freescale Semiconductor, Inc