DSP56857 datasheet(363/662 Pages) FREESCALE

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Interrupt Operation Description

Enhanced Synchronous Serial Interface (ESSI), Rev. 4

Freescale Semiconductor

12-63

12.12 Interrupts

The ESSI can generate up to six interrupt vectors, listed in Table 12-27.

12.13 Interrupt Operation Description

12.13.1 Receive Data With Exception

This interrupt can occur when receive interrupts are enabled via the RIE bit of the SCR2 register.

When a data word is ready to transfer from the RXSR register to the SRX register and the

previous SRX register data has not yet been read, the ROE bit is set and the exception interrupt

will occur instead of the normal receive data interrupt. When the receive FIFO is enabled this

interrupt will not occur until the RFF bit has been set, indicating the FIFO is full. The ROE bit is

cleared when the SSR is read verifying the ROE bit is set before reading the SRX register data.

SCR3

TFEN

RFEN

REFS

RFSL

RFSI

RSCKP

RSHFD

DIV4DIS

SCR4

SCD0

SCD1

SCD2

SDKD

SSC1

Table 12-27.

Interrupt Summary

Interrupt

Source

Description

INTR + $0

Receiver

Receive data with exception

INTR + $2

Receiver

Receive data

INTR + $4

Receiver

Receive last slot interrupt. This interrupt may not be present in all

implementations of the ESSI.

INTR + $6

Transmitter

Transmit data with exception

INTR + $8

Transmitter

Transmit data

INTR + $10

Transmitter

Transmit last slot interrupt. This interrupt may not be present in all

implementations of the ESSI.

Table 12-26.

ESSI Control Bits Requiring

Reset Before Change (Continued)

Control Register

Bit

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