DSP56857 datasheet(365/662 Pages) FREESCALE

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DSP56857 데이터시트(PDF) 365 Page - Freescale Semiconductor, Inc

부품명	DSP56857

상세설명	Digitial Signal Controller

PDF	662 Pages

Scroll/Zoom	100%

제조업체	FREESCALE [Freescale Semiconductor, Inc]

홈페이지	http://www.freescale.com

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365 / 662 page

User Notes

Enhanced Synchronous Serial Interface (ESSI), Rev. 4

Freescale Semiconductor

12-65

12.13.6 Transmit Last Slot (TLS)

This interrupt occurs when the ESSI is in the Network mode at the beginning of the last slot of

the transmit frame. The TLS bit is also set at this time. This exception occurs regardless of the

Transmit Mask Register setting. This interrupt and the TLS bit are cleared by writing 1 to the

TLS bit of the SSR.

12.14 User Notes

12.14.1 External Frame Sync Setup

When using external frame syncs, there must be at least four clocks after enabling the

transmitter/receiver and before the first frame sync.

12.14.2 Maximum External Clock Rate

The maximum allowable rate for an external clock source is one fourth of the peripheral clock.

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