DSP56857 datasheet(369/662 Pages) FREESCALE

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Features

Quad Timer (TMR), Rev. 4

Freescale Semiconductor

13-3

13.1 Introduction

The Quad Timer (TMR) module contains four identical counter/timer groups. Each 16-bit

counter/timer group contains a

•

Prescaler

•

Counter

•

Load register

•

Hold register

•

Capture register

•

Two Compare registers

•

Two Status and Control registers

All except the prescaler are read/write registers.

Note:

This document uses the terms Timer and Counter interchangeably because the

counter/timers may perform either or both tasks.

The Load register provides the initialization value to the counter when the counter’s terminal

value has been reached. Hold registers capture the counter’s value the instant any Counter

enables an external signal to take a snapshot of the counter’s current value. The TMR_CMP1 and

TMR_CMP2 registers provide the values to which the counter is compared. If a match occurs, the

OFLAG signal can be set, cleared, or toggled. At match time, an interrupt is generated if enabled.

The Prescaler provides different IPBus Clock time bases useful for clocking the counter. The

Counter provides the ability to count internal or external events. Input pins are shared within a

Timer module.

13.2 Features

The Quad TMR module design includes these distinctive capabilities:

•

Four, 16-bit counters/timers

•

Count up/down

•

Counters are cascadable

•

Count modulo can be programmed

•

Maximum count rate equals peripheral clock for external clocks

•

Maximum count rate equals peripheral clock for internal clocks

•

Count once or repeatedly

•

Counters can be preloaded

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