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JTAG Port Architecture

5685X Digital Signal Controller User Manual, Rev. 4

17-6

Freescale Semiconductor

17.5 JTAG Port Architecture

The TAP Controller is a simple state machine used to sequence the JTAG port through its varied

operations:

•

Serially shift in or out a JTAG port command

•

Update and decode the JTAG port Instruction Register (JTAGIR)

•

Serially input or output a data value

•

Update a JTAG port or EOnCE module register

Note:

The JTAG port supervises the shifting of data into and out of the EOnCE module

through TDI and TDO pins respectively. In this case, the shifting is guided by the same

controller used when shifting JTAG information.

The JTAG block diagram is illustrated in Figure 17-1. The JTAG port has four read/write

registers:

1. Instruction Register (JTAGIR)

2. Chip Identification (CID) register

3. Bypass Register (JTAGBR)

4. Boundary Scan Register (BSR)

Access to the EOnCE registers is described in the DSP56800E Reference Manual.

17.5.1 JTAG Instruction Register (JTAGIR) and Decoder

The TAP Controller contains a 8-bit instruction register. The instruction is presented to an

instruction decoder during the update-instruction register state. Please see Section 17.8 for a

description of the TAP Controller operating states. The instruction decoder interprets and

executes the instructions according to the conditions defined by the TAP Controller state

machine.

The 5685x includes the three mandatory public instructions:

1. BYPASS

2. SAMPLE/PRELOAD

3. EXTEST

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