DSP56857 datasheet(578/662 Pages) FREESCALE

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Appendix B - Programmer’s Sheets, Rev. 4

Freescale Semiconductor

B-76

Preliminary

9 of 16

ESSI Control Register 4 (SCR4)

denotes Reserved Bits

Bits

Name

Description

TXSFO

Transmit Status Flag Control 0

The indicated transmitter does not affect the status bits

The indicated transmitter status will affect the TFF, TDE, TUE, and TFE status bits

TXSF1

Transmit Status Flag Control 1

The indicated transmitter does not affect the status bits

The indicated transmitter status will affect the TFF, TDE, TUE, and TFE status bits

TXSF2

Transmit Status Flag Control 2

The indicated transmitter does not affect the status bits

The indicated transmitter status will affect the TFF, TDE, TUE, and TFE status bits

SSC1

Select SC1

This bit controls the functionality of the SC1 signal and is used only if SYN = 1 and TE2 = 0

The SC1 acts as the serial I/O flag (IF1/OF1)

When configured as an output (SCD1 = 1), the SC1 signal acts as the transmitter 0

driver-enable, enabling an external buffer for the transmitter 0 output

SCKD

Clock Source Direction

This bit configures the source of the clock signal used to clock the transmit shift register in

Asynchronous mode and both Transmit and Receive Shift Registers are in Synchronous mode

SCK pin is configured as an input. This pin is used as the clock source

Internal transmit clock generator is selected. This clock is output on the SCK pin

SCD2

Serial Control Direction 2

This bit controls the direction of the SC2 pin

SC2 is an input

SC2 is an output

ESSI Control

Base + $7

Bits

Read

TXSFO TXSF1 TXSF2

SSC1 SCKD SCD2 SCD1 SCD0 OF1

OF0

Write

Reset

000

ESSI

See the following page for continuation of this register

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