DSP56857 datasheet(181/662 Pages) FREESCALE

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Introduction

Overview, Rev. 4

Freescale Semiconductor

8-3

8.1 Introduction

The Interrupt Controller (ITCN) is responsible for arbitrating all interrupt requests according to

the priority level of the each request. This includes all external interrupt sources, such as IRQA,

IRQB, and so on, peripheral generated interrupt requests and core generated interrupt requests.

After arbitration, the interrupt controller will compare the priority of the current interrupt request

with the current priority level of the core and if the request has higher priority to generate a

single enabled interrupt request signal to the core.

There are five levels of interrupt priority provided by the 56800E core, illustrated in Table 8-1:

1. LP = the lowest level is generated by the SWILP instruction

2. Level 0 = maskable with the lowest priority of the three maskable interrupts

3. Level 1 = maskable

4. Level 2 = maskable

5. Level 3 = the highest priority is a non-maskable interrupt

Device interrupt priority levels are programmable via the Interrupt Priority Register (IPR).

The interrupt controller is also responsible for generating the vector address of the current

interrupt request. This is based on the Vector Address Base (VAB) register and the event

initiating the request. The interrupt controller predefines the Vector Table offsets for all possible

interrupt sources and will generate the Vector Address of the request by adding the

programmable VAB register to the Vector Table offset.

External interrupt sources such as IRQA and IRQB are programmable to either level sensitive or

edge triggered. Level sensitive interrupts remain active as long as the input remains low and are

cleared when the input level goes high. The edge sensitive interrupts are latched as pending on

the high-to-low transition of the interrupt input and are cleared when the interrupt is serviced.

Table 8-1. Interrupt Priority Level

IPL

Description

Priority

Interrupt Sources

Maskable

Lowest

SWILP instruction

Maskable

—

On-chip peripherals, IRQA and IRQB,

SWI #0 instruction

Maskable

—

On-chip peripherals, IRQA and IRQB,

SWI #1 instruction, EOnCE interrupts

Maskable

—

On-chip peripherals, IRQA and IRQB,

SWI #2 instruction, EOnCE interrupts

Non-maskable

Highest

Illegal instruction, HWS overflow,

SWI #3 instruction, EOnCE interrupts,

Misaligned data access

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