V62SLASH13624-01XE-R datasheet(33/77 Pages) TI1

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MSP430F2132-EP

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SLAS913A – JULY 2013 – REVISED AUGUST 2013

Product Folder Links: MSP430F2132-EP

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(1)

The DCO wake-up time must be considered in LPM3 and LPM4 for baud rates above 1 MHz.

(2)

Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

5.25 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

CONDITIONS

VCC

MIN

TYP

MAX

UNIT

fUSCI

USCI input clock frequency

Internal: SMCLK, ACLK

External: UCLK

Duty cycle = 50% ± 10%

fSYSTEM

MHz

fmax,BITCLK

Maximum BITCLK clock frequency

(equals baud rate in MBaud)(1)

2.2 V, 3 V

MHz

tτ

UART receive deglitch time(2)

2.2 V

150

3 V

100

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).

For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.

(2)

Not ensured for TA > 105°C.

5.26 USCI (SPI Master Mode)

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Figure 4 and Figure 5)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

fUSCI

USCI input clock frequency

SMCLK, ACLK

Duty cycle = 50% ± 10%

fSYSTEM

MHz

tSU,MI

SOMI input data setup time

2.2 V

110

3 V

tHD,MI

SOMI input data hold time

2.2 V

3 V

tVALID,MO

SIMO output data valid time(2)

UCLK edge to SIMO valid,

CL = 20 pF

2.2 V

3 V

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).

For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.

(2)

Not ensured for TA > 105°C.

5.27 USCI (SPI Slave Mode)

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Figure 6 and Figure 7)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

tSTE,LEAD

STE lead time, STE low to clock

2.2 V, 3 V

tSTE,LAG

STE lag time, Last clock to STE high

2.2 V, 3 V

tSTE,ACC

STE access time, STE low to SOMI data out

2.2 V, 3 V

tSTE,DIS

STE disable time, STE high to SOMI high

impedance

2.2 V, 3 V

tSU,SI

SIMO input data setup time

2.2 V

3 V

tHD,SI

SIMO input data hold time

2.2 V

3 V

tVALID,SO

SOMI output data valid time(2)

UCLK edge to SOMI valid,

CL = 20 pF

2.2 V

110

3 V

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