V62SLASH13624-01XE-R datasheet(62/77 Pages) TI1

62 / 77 page

Direction

0: Input

1: Output

P2SEL.7

P2DIR.7

P2IN.7

P2IRQ.7

Module X IN

Module X OUT

P2OUT.7

Interrupt

Edge Select

Set

P2SEL.7

P2IES.7

P2IFG.7

P2IE.7

DVSS

DVCC

Pad Logic

Bus

Keeper

P2.7/XOUT/CA7

LFXT1CLK

P2.6/XIN/CA6

LFXT1 off

BCSCTL3.LFXT1Sx = 11

From P2.6/XIN

From

Comparator

To Comparator

P2SEL.6

CAPD.7

P2REN.7

MSP430F2132-EP

SLAS913A – JULY 2013 – REVISED AUGUST 2013

www.ti.com

Product Folder Links: MSP430F2132-EP

Submit Documentation Feedback

(1)

X = Don't care

(2)

Setting the CAPD.x bit disables the output driver as well as the input to prevent parasitic cross currents when applying analog signals.

Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin, regardless

of the state of the associated CAPD.x bit.

6.10 Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger

Table 25. Port P2 (P2.7) Pin Functions

PIN NAME (P2.x)

FUNCTION

CONTROL BITS AND SIGNALS(1)

CAPD.7

P2DIR.7

P2SEL.7

P2SEL2.x = 0

P2.7/XOUT/CA7

P2.7 (I/O)

I: 0, O: 1

XOUT (default)

CA7(2)

V62/13624-01XE-R 데이터시트(PDF) 62 Page - Texas Instruments

V62/13624-01XE-R 데이터시트(HTML) 62 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

데이터시트 다운로드

링크 URL