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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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NM1282KSLAXAL 데이터시트(PDF) 96 Page - Nanya Technology Corporation. |
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NM1282KSLAXAL 데이터시트(HTML) 96 Page - Nanya Technology Corporation. |
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96 / 120 page  Version 1.3 96 Nanya Technology Corp. 06/2018 All Rights Reserved. © 2Gb SLC NAND + 2Gb LPDDR2 NM1282KSLAXAL NTC Proprietary Level: Property Symbol Parameter min/ max min tCK Speed Grade Unit 1066 Write parameters tDH DQ and DM input hold time (VREF based) min 210 ps tDS DQ and DM input setup time (VREF based) min 210 ps tDIPW DQ and DM input pulse width min 0.35 tCK(avg) tDQSS Write command to 1st DQS latching transition min 0.75 tCK(avg) max 1.25 tCK(avg) tDQSH DQS input high-level width min 0.4 tCK(avg) tDQSL DQS input low-level width min 0.4 tCK(avg) tDSS DQS falling edge to CK setup time min 0.2 tCK(avg) tDSH DQS falling edge hold time from CK min 0.2 tCK(avg) tWPST Write postamble min 0.4 tCK(avg) tWPRE Write preamble min 0.35 tCK(avg) Symbol Parameter min/ max min tCK Speed Grade Unit 1066 CKE input parameters tCKE CKE min. pulse width (high and low) min 3 3 tCK(avg) tISCKE CKE input setup time min 0.25 tCK(avg) tIHCKE CKE input hold time min 0.25 tCK(avg) Command / Address Input parameters tIH Address and Control input hold time min 220 ps tIS Address and Control input setup time min 220 ps tIPW Address and Control input pulse width min 0.4 tCK(avg) Mode register parameters tMRR MODE Register Read command period min 2 2 tCK(avg) tMRW MODE Register Write command period min 5 5 tCK(avg) SDRAM core parameters RL Read Latency min 3 8 tCK(avg) WL Write Latency min 1 4 tCK(avg) tCKESR CKE minimum pulse width during SELF REFRESH (low pulse width during SELF REFRESH) min 3 15 ns tXSR Exit SELF REFRESH to first valid command (min) min 2 tRFCAB +10 ns |
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