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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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NM1282KSLAXAL 데이터시트(PDF) 22 Page - Nanya Technology Corporation. |
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NM1282KSLAXAL 데이터시트(HTML) 22 Page - Nanya Technology Corporation. |
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22 / 120 page  Version 1.3 22 Nanya Technology Corp. 06/2018 All Rights Reserved. © 2Gb SLC NAND + 2Gb LPDDR2 NM1282KSLAXAL NTC Proprietary Level: Property Multi Page Read Operation The device has a Multi Page Read operation and Multi Page Read with Data Cache operation. (1) Multi Page Read without Data Cache The sequence of command and address input is shown below. Same page address (PA0 to PA5) within each district has to be selected. For X8 : The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising edge of in the 30h command input cycle (after the 2 Districts address information has been latched). The device will be in the Busy state during this transfer period. After the transfer period, the device returns to Ready state. Serial data can be output synchronously with the clock from the start address designated in the address input cycle. |
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