56F8167 datasheet(27/184 Pages) FREESCALE

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Signal Pins

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

GPIOD2

(CS4)

Input/

Output

Input,

pull-up

enabled

Port D GPIO — These four GPIO pins can be individually

programmed as input or output pins.

Chip Select — CS4 - CS7 may be programmed within the EMI

module to act as chip selects for specific areas of the external

memory map.

Depending upon the state of the DRV bit in the EMI bus control

inactive.

Most designs will want to change the DRV state to DRV = 1 instead

of using the default setting.

At reset, these pins are configured as GPIO.

To deactivate the internal pull-up resistor, clear the appropriate

GPIO bit in the GPIOD_PUR register.

Example: GPIOD2, clear bit 2 in the GPIOD_PUR register.

GPIOD3

(CS5)

GPIOD4

(CS6)

GPIOD5

(CS7)

TXD0

(GPIOE0)

Output

Input/

Output

In reset,

output is

disabled,

pull-up is

enabled

Transmit Data — SCI0 transmit data output

Port E GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is SCI output.

To deactivate the internal pull-up resistor, clear bit 0 in the

GPIOE_PUR register.

RXD0

(GPIOE1)

Input

Input/

Output

Input,

pull-up

enabled

Receive Data — SCI0 receive data input

Port E GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is SCI output.

To deactivate the internal pull-up resistor, clear bit 1 in the

GPIOE_PUR register.

Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA

Signal

Name

No.

Ball No.

Type

State

During

Reset

Signal Description

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