56F8167 datasheet(29/184 Pages) FREESCALE

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Signal Pins

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

TRST

136

Schmitt

Input

Input,

pulled high

internally

Test Reset — As an input, a low signal on this pin provides a

reset signal to the JTAG TAP controller. To ensure complete

hardware reset, TRST should be asserted whenever RESET is

asserted. The only exception occurs in a debugging environment

when a hardware device reset is required and the JTAG/EOnCE

module must not be reset. In this case, assert RESET, but do not

assert TRST.

To deactivate the internal pull-up resistor, set the JTAG bit in the

SIM_PUDR register.

PHASEA0

(TA0)

(GPIOC4)

155

Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input/

Output

Input,

pull-up

enabled

Phase A — Quadrature Decoder 0, PHASEA input

TA0 — Timer A, Channel 0

Port C GPIO — This GPIO pin can be individually programmed

as an input or output pin.

After reset, the default state is PHASEA0.

To deactivate the internal pull-up resistor, clear bit 4 of the

GPIOC_PUR register.

PHASEB0

(TA1)

(GPIOC5)

156

Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input/

Output

Input,

pull-up

enabled

Phase B — Quadrature Decoder 0, PHASEB input

TA1 — Timer A, Channel

Port C GPIO — This GPIO pin can be individually programmed

as an input or output pin.

After reset, the default state is PHASEB0.

To deactivate the internal pull-up resistor, clear bit 5 of the

GPIOC_PUR register.

Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA

Signal

Name

No.

Ball No.

Type

State

During

Reset

Signal Description

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