56F8167 datasheet(149/184 Pages) FREESCALE

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External Memory Interface Timing

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

149

Preliminary

DCAOE and DCAEO are calculated as follows:

The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters

contain two sets of numbers to account for this difference. Use the “Wait States Configuration” column

of Table 10-16 to make the appropriate selection.

Figure 10-4 External Memory Interface Timing

Note:

When multiple lines are given for the same wait state configuration, calculate each and then select the

smallest or most negative.

DCAOE =

0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to

÷ 1

0.0 all other cases

DCAEO =

MIN XTAL duty cycle - 0.5, if ZSRC selects prescaler clock and the prescaler is set to

÷ 1

0.0 all other cases

Example of DCAOE and DCAEO calculation:

Assuming prescaler is set for

÷ 1 and prescaler clock is selected by ZSRC, if XTAL duty cycle

ranges between 45% and 60% high;

DCAOE = .50 - .60 = - 0.1

DCAEO = .45 - .50 = - 0.05

tDRD

tRDD

tAD

tDOH

tDOS

tDWR

tRDWR

tWAC

tWRRD

tWR

tAWR

tWRWR

tARDD

tRDA

tRDRD

tRD

tARDA

Data Out

Data In

A0-Axx,CS

D0-D15

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

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