CS7620 datasheet(12/70 Pages) CIRRUS

12 / 70 page

CS7620

DS301PP2

The open-loop transfer function of the black level

adjustment loop is

blk_gain = 1, 2, 4, or 8

where blk_gain is programmable through a register

and n = # of black pixels during clamp time, which

is also programmable. The value of Kxn will deter-

mine the open-loop gain of the system. The settling

time for the loop can be calculated using the fol-

lowing formula:

For offset range=1 (reg 06h, bit 0)

For offset range =0

During fixed gain mode the time constant is a little

different.

In order to achieve no ringing in the settling use,

for offset range = 1, and

for offset

range = 0.

The 9 MSBs of the black level accumulator can be

read or written through a register. If written, the

LSBs are set to zero. The black level is set to “8” in

a 10-bit digital output representation. In a 13-bit

representation, it is set to “64.” The power-up de-

fault value in the accumulator is at mid level.

Also note that the black level adjust loop can be

disabled. In addition, the black level can be pro-

grammed through the serial port.

3.2

Gain Adjust Block

In order to increase the dynamic range of the ADC,

a variable gain, whose value is determined by the

signal level, is applied to each pixel. This allows

for 13 bits of dynamic range and 10 bits of resolu-

tion after accounting for the significance of the

ADC output bits. The gain applied in the analog is

illustrated in the transfer curve in Figure 7. Once

the signal is digitized, the gain adjust block uses the

gain information for a given pixel word and shifts

its bits accordingly. For example, using the default

full scale level of 1.07V, if Vin = 0.3 V, the VGA

would choose a gain of 2X so the ADC input is 0.6

V. The 10-bit output of the ADC (with no black

level) is (0.6/1.07) × 1024 = 574, or “1000111110.”

in binary. The gain adjust block will take this value

For a fixed gain of 1:

For a fixed gain of 2:

()

–

-------------

256

---------blk_gain

1nK

–

()

---------------------------

–



 1

-----





-------

–





----------------------------

–







-----





-------

–





----------------------------

–







-----





-------

–





----------------------------

–







-----





For a fixed gain of 4:

For a fixed gain of 8:

-------

–





----------------------------

–







-----





1nK

–

()

---------------------------

–



 1

-----





----

≤

-------

≤

CS7620 데이터시트(PDF) 12 Page - Cirrus Logic

CS7620 데이터시트(HTML) 12 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

데이터시트 다운로드

링크 URL