CS7620 datasheet(15/70 Pages) CIRRUS

15 / 70 page

CS7620

DS301PP2

The output of the compander is available at the pins

DOUT<9:0> and it makes transitions either at the

falling or rising edges of the pixel rate clock CL-

KO, controlled by a register bit. The Falling edge

option is shown in Figure 14.

Two options exist for outputting data. The first op-

tion will output the pixel rate clock on the CLKO

pin. The polarity of the pixel clock out of the pin is

programmable so that the user may choose the ap-

propriate clock edge to latch in the data. Based on

the RD_OUT and HSYNC signals, the user will be

able to determine when he is over active pixels. The

second option will output a data_valid signal on the

CLKO pin that is synchronous with the input clock

(Figure 15). The data_valid signal will only toggle

over active pixels. The user may then latch the data

during this valid time. Note: DATA_VALID mode

cannot be used if the system clock runs at the pixel

rate.

3.4

Timing Generator

There are three timing options available with the

CS7620. The chip may produce all the vertical and

horizontal timing for the imager, only the horizon-

tal timing, or the chip may be used in a complete

slave mode and not produce any of the CCD timing

at all. Each will be discussed in detail in this sec-

tion.

3.4.1

Vertical and Horizontal Timing

Mode

To select this option, the user must tie the

BYPASS_PLL pin low and select the proper inter-

nal timing mode in the timing mode register. The

CS7620 is the master of the clocking. It will pro-

vide vertical outputs and horizontal outputs. In this

mode, the user must control two signals. The first is

the master PWR_DN signal. When this signal is

high, all of the CS7620 powers down except for the

1023

CODE_IN

CODE_OUT

8191

SLOPE1

SLOPE2

SLOPE3

SLOPE4

OFFSET2

OFFSET3

OFFSET4

OFFSET1

(x2,y2)

(x1,y1)

(x3,y3)

Figure 13. 13-to-10 bit compander

Figure 14. CS7620 output data and clocks

CLKO

DOUT<9:0>

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