STM8S datasheet(91/467 Pages) STMICROELECTRONICS

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RM0016

Clock control (CLK)

104

9.9.2

External clock register (CLK_ECKR)

Address offset: 0x01

Reset value: 0x00

Bit 2 FHWU: Fast wakeup from Halt/Active-halt modes

This bit is set and cleared by software.

0: Fast wakeup from Halt/Active-halt modes disabled

1: Fast wakeup from Halt/Active-halt modes enabled

Bit 1 HSIRDY: High speed internal oscillator ready

This bit is set and cleared by hardware.

0: HSI clock not ready

1: HSI clock ready

Bit 0 HSIEN: High speed internal RC oscillator enable

This bit is set and cleared by software. It is set by hardware whenever the HSI oscillator is required,

for example:

–

When activated as safe oscillator by the CSS

–

When switching to HSI clock (see CLK_SWR register)

–

When HSI is selected as the active CCO source (see CLK_CCOR register)

It cannot be cleared when HSI is selected as clock master (CLK_CMSR register), as active CCO

source or if the safe oscillator (AUX) is enabled.

0: High-speed internal RC off

1: High-speed internal RC on

654

3210

Reserved

HSERDY

HSEEN

Bits 7:2 Reserved, must be kept cleared.

Bit 1 HSERDY: High speed external crystal oscillator ready

This bit is set and cleared by hardware.

0: HSE clock not ready

1: HSE clock ready (HSE clock is stabilized and available)

Bit 0 HSEEN: High speed external crystal oscillator enable

This bit is set and cleared by software. It can be used to switch the external crystal oscillator on or

off. It is set by hardware in the following cases:

–

When switching to HSE clock (see CLK_SWR register)

–

When HSE is selected as the active CCO source (see CLK_CCOR register)

It cannot be cleared when HSE is selected as clock master (indicated in CLK_CMSR register) or as

the active CCO source.

0: HSE clock off

1: HSE clock on

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