STM8S datasheet(178/467 Pages) STMICROELECTRONICS

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16-bit advanced control timer (TIM1)

RM0016

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DocID14587 Rev 14

The OPM waveform is defined by writing the compare registers (taking into account the

clock frequency and the counter prescaler) as follows:

•

The tDELAY is defined by the value written in the TIM1_CCR1 register

•

The tPULSE is defined by the difference between the auto-reload value and the compare

value (TIM1_ARR - TIM1_CCR1).

•

To build a waveform with a transition from 0 to 1 when a compare match occurs and a

transition from 1 to 0 when the counter reaches the auto-reload value, enable PWM

mode 2 by writing OCiM = 111 in the TIM1_CCMR1 register. Alternatively, enable the

preload registers by writing OC1PE = 1 in the TIM1_CCMR1 register and ARPE = 0 in

the TIM1_CR1 register (optional). In this case, write the compare value in the

TIM1_CCR1 register and write the auto-reload value in the TIM1_ARR register. Then,

generate an update by setting the UG bit and wait for an external trigger event on TI2.

CC1P is written to 0 in this example.

In the example outlined above, the DIR and CMS bits in the TIM1_CR1 register should be

low.

As only one pulse is required, write 1 in the OPM bit in the TIM1_CR1 register to stop the

counter at the next UEV (when the counter rolls over from the auto-reload value back to 0).

Particular case: OCi fast enable

In one-pulse mode, the edge detection on the TIi input sets the CEN bit which enables the

counter. Then, a comparison between the counter and the compare value makes the output

toggle. However, several clock cycles are needed for these operations and this affects the

the minimum delay (tDELAY min) that can be obtained.

To output a waveform with the minimum delay, set the OCiFE bits in the TIM1_CCMRi

registers. OCiREF (and OCi) are forced in response to the stimulus, without taking the

comparison into account. The new level of OCiREF (and OCi) is the same as if a compare

match had occured. The OCiFE bits acts only if the channel is configured in PWM1 or

PWM2 mode.

Complementary outputs and deadtime insertion

TIM1 can output two complementary signals per channel. It also manages the switching-off

and switching-on instants of the outputs (see Figure 31: TIM1 general block diagram on

page 140).

This time is generally known as deadtime. Deadtimes must be adjusted depending on the

characteristics of the devices connected to the outputs (example, intrinsic delays of level-

shifters, delays due to power switches).

The polarity of the outputs can be selected (main output OCi or complementary OCi N)

independently for each output. This is done by writing to the CCi P and CCi NP bits in the

TIM1_CCERi registers.

The complementary signals OCi and OCi N are activated by a combination of several

control bits: The CCi E and CCi NE bits in the TIM1_CCERi register and, if the break feature

is implemented, the MOE, OISi, OISi N, OSSI, and OSSR bits in the TIM1_BKR register.

Refer to Table 38: Output control for complementary OCi and OCiN channels with break

feature on page 207 for more details. In particular, the deadtime is activated when switching

to the IDLE state (when MOE falls to 0).

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