STM8S datasheet(197/467 Pages) STMICROELECTRONICS

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RM0016

16-bit advanced control timer (TIM1)

261

17.7.8

Event generation register (TIM1_EGR)

Address offset: 0x07

Reset value: 0x00

Bit 2 CC2OF: Capture/compare 2 overcapture flag

Refer to CC1OF description

Bit 1 CC1OF: Capture/compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input capture

mode. It is cleared by software by writing it to 0.

0: No overcapture has been detected

1: The counter value has been captured in TIM1_CCR1 register while CC1IF flag was already set

Bit 0 Reserved, must be kept cleared.

654

3210

COMG

CC4G

CC3G

CC2G

CC1G

www

Bit 7 BG: Break generation

This bit is set by software to generate an event. It is automatically cleared by hardware.

0: No action

1: A break event is generated. The MOE bit is cleared and the BIF flag is set. An interrupt is

generated if enabled by the BIE bit.

Bit 6 TG: Trigger generation

This bit is set by software to generate an event. It is automatically cleared by hardware.

0: No action

1: The TIF flag is set in TIM1_SR1 register. An interrupt is generated if enabled by the TIE bit.

Bit 5 COMG: Capture/compare control update generation

This bit can be set by software and is automatically cleared by hardware.

0: No action

1: When the CCPC bit in the TIM1_CR2 register is set, it allows the CCiE, CCiNE CCiP, CCiNP, and

OCiM bits to be updated.

Note: This bit acts only on channels that have a complementary output.

Bit 4 CC4G: Capture/compare 4 generation

Refer to CC1G description.

Bit 3 CC3G: Capture/compare 3 generation

Refer to CC1G description.

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