STM8S datasheet(242/467 Pages) STMICROELECTRONICS

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16-bit general purpose timers (TIM2, TIM3, TIM5)

RM0016

242/467

DocID14587 Rev 14

18.6.12

Capture/compare enable register 2 (TIMx_CCER2)

Address offset: 0x09 or 0x0B (TIM2), 0x0B (TIM5); for TIM2 address see Section

Reset value: 0x00

Note:

This register is not available in TIM3.

18.6.13

Counter high (TIMx_CNTRH)

Address offset: 0x0A or 0x0C (TIM2), 0x08 (TIM3), 0x0C (TIM5); for TIM2 address see

Section

Reset value: 0x00

Bits 2:3 Reserved

Bit 1 CC1P: Capture/compare 1 output polarity

CC1 channel configured as output:

0: OC1 active high

1: OC1 active low

CC1 channel configured as input for capture function (see Figure 64):

0: Capture is done on a rising edge of TI1F or TI2F

1: Capture is done on a falling edge of TI1F or TI2F

Bit 0 CC1E: Capture/Compare 1 output Enable.

CC1 channel configured as output:

0: Off - OC1 is not active.

1: On - OC1 signal is output on the corresponding output pin.

CC1 channel configured as input:

In this case, this bit determines if a capture of the counter value can be made in the input

capture/compare register 1 (TIMx_CCR1) or not.

0: Capture disabled

1: Capture enabled

654

3210

Reserved

CC3P

CC3E

rrw

Bits 7:2 Reserved

Bit 1 CC3P: Capture/compare 3 output polarity

Refer to CC1P description.

Bit 0 CC3E: Capture/compare 3 output enable

Refer to CC1E description.

654

3210

CNT[15:8]

Bits 7:0 CNT[15:8]: Counter value (MSB)

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