STM8S datasheet(265/467 Pages) STMICROELECTRONICS

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RM0016

Serial peripheral interface (SPI)

287

Clock phase and clock polarity

Four possible timing relationships may be chosen by software, using the CPOL and CPHA

bits. The CPOL (clock polarity) bit controls the steady state value of the clock when no data

is being transferred. This bit affects both master and slave modes. If CPOL is reset, SCK pin

has a low level idle state. If CPOL is set, SCK pin has a high level idle state.

Note:

Make sure the SPI pin is configured at the idle state level of the SPI in order to avoid

generating an edge on the SPI clock pin when enabling or disabling the SPI cell.

If CPHA (clock phase) bit is set, the second edge on the SCK pin (falling edge if the CPOL

bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on

the occurrence of the first clock transition. If CPHA bit is reset, the first edge on the SCK pin

(falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the MSBit capture strobe.

Data is latched on the occurrence of the second clock transition.

The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data

capture clock edge.

Figure 93 shows an SPI transfer with the four combinations of the CPHA and CPOL bits.

The diagram may be interpreted as a master or slave timing diagram where the SCK pin,

the MISO pin, the MOSI pin are directly connected between the master and the slave

device.

Note:

Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.

Master and slave must be programmed with the same timing mode.

The idle state of SCK must correspond to the polarity selected in the SPI_CR1 register (by

pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

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