STM8S datasheet(291/467 Pages) STMICROELECTRONICS

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RM0016

Inter-integrated circuit (I2C) interface

319

21.4

I2C functional description

By default the I2C interface operates in Slave mode. To switch from default Slave mode to

Master mode a Start condition generation is needed.

21.4.1

I2C slave mode

The peripheral input clock must be programmed in the I2C_FREQR register in order to

generate correct timings. The peripheral input clock frequency must be at least:

•

1 MHz in Standard mode

•

4 MHz in Fast mode

As soon as a start condition is detected, the address is received from the SDA line and sent

to the shift register. Then it is compared with the address of the interface (OAR1L and OAR2

if ENDUAL = 1) or the General Call address (if ENGC = 1).

Note:

In 10-bit addressing mode, the comparison includes the header sequence (11110xx0),

where xx denotes the two most significant bits of the address.

Header or address not matched: the interface ignores it and waits for another Start

condition.

Header matched (10-bit mode only): the interface generates an acknowledge pulse if the

ACK bit is set and waits for the 8-bit slave address.

Address matched: the interface generates in sequence:

•

An acknowledge pulse if the ACK bit is set

•

The ADDR bit is set by hardware and an interrupt is generated if the ITEVTEN bit is

set.

In 10-bit mode, after receiving the address sequence the slave is always in Receiver mode.

It will enter Transmitter mode on receiving a repeated Start condition followed by the header

sequence with matching address bits and the least significant bit set (11110xx1).

The TRA bit indicates whether the slave is in Receiver or Transmitter mode.

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